`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/12 20:37:47
// Design Name: 
// Module Name: demo
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module demo(
    input sys_clk,   //时钟输入 50MHz
    input [11:0] sw,//拨码开关输入
    
    input [3:0] col,
    output [3:0] row,//按键扫描  col row
    
    output [11:0] led,   //LED输出

    output [7:0] seg,//数码管段码输
    output [5:0] an,//数码管位码输
    
    output Hsync,   //VGA信号输出
    output Vsync,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,

    input vauxp7, vauxn7,  // 模拟输入通道6
    input vauxp8, vauxn8   // 模拟输入通道7

    );

wire [4:0] key_value;
reg [0:1055] canvas [0:623];

reg[23:0] disp_data; //显示数据寄存器
  

wire rst_n;
assign rst_n = sw[11];


/*****************1---MMCM产生系统时钟********************/
wire clk_50m;
  clk_wiz_1 u_clk
   (
    // Clock out ports
    .clk_out1(clk_6m),     // output clk_out1
    .clk_out2(clk_50m),     // output clk_out2
    // Status and control signals
    .resetn(rst_n), // input resetn
   // Clock in ports
    .clk_in1(sys_clk)      // input clk_in1
);





/*****************2---按键检测********************/
key key_scan(
    .clk(clk_50m),
    .col(col),
    .row(row),
    .btn_clicked_num(key_value),
    .rst_n(rst_n)
);
/*****************3---数码管显示********************/
display mydisp(
	.dispdata(disp_data),
	.clk(clk_50m),
	.seg(seg),
	.an(an),
    .rst_n(rst_n)
 );

/*****************4---XADC信号采集********************/
//0、XADC采集部分
    //(1)不更新
wire [11:0] value_temp;
wire [11:0] value_vccint;
wire [11:0] value_vccbram;
    //(2)原始数据
wire adc_clk;
wire [11:0] value_ch1;
wire [11:0] value_ch2;
    //(3)零插数据
wire adc_insert_clk; 
wire [11:0] value_insert_ch1;
wire [11:0] value_insert_ch2;
    //(4)滤波数据
wire adc_filter_clk_ch1; 
wire adc_filter_clk_ch2;
wire [11:0] value_filter_ch1;
wire [11:0] value_filter_ch2;
    //(5)触发数据
wire [31:0] Trigger_cnt  ;
wire [11:0] Trigger_data ;
wire        Trigger_occur;
wire        Trigger_clk  ;
    //(6)其他
wire [7:0] state;
my_xadc u_my_xadc(
    .dclk           (clk_50m),
    .rst_n          (rst_n),
    .ch1_p          (vauxp7),
    .ch1_n          (vauxn7),
    .ch2_p          (vauxp8),
    .ch2_n          (vauxn8),
    
    .value_temp     (value_temp),
    .value_vccint   (value_vccint),
    .value_vccbram  (value_vccbram),

    .adc_clk        (adc_clk),
    .value_ch1      (value_ch1),
    .value_ch2      (value_ch2),

    .adc_insert_clk (adc_insert_clk),
    .value_insert_ch1(value_insert_ch1),
    .value_insert_ch2(value_insert_ch2),

    .adc_filter_clk_ch1(adc_filter_clk_ch1),
    .adc_filter_clk_ch2(adc_filter_clk_ch2),
    .value_filter_ch1  (value_filter_ch1),
    .value_filter_ch2  (value_filter_ch2),

    .Trigger_cnt    (Trigger_cnt),
    .Trigger_data   (Trigger_data),
    .Trigger_occur  (Trigger_occur),
    .Trigger_clk    (Trigger_clk),

    .state          (state)
);

/*****************************5---状态切换***********************************/
reg [2:0] sp=0;
reg [3:0] inp=0;
reg[3:0] present_state=1;
parameter idle=1,inputdata=2,sign1=3;//状态机
parameter negate=12,enter=11,next=10,add=13,sub=14,mltp=15;
wire divclk;
    divider #(
        .OUT_CLK(1000),
        .CLK(50000000)
    )
    sttdivclk(
        .clk (clk_50m),
        .rst_n(rst_n),
        .out_clk(divclk)
    );

always @ (posedge divclk)
  begin         
   case(present_state)
	   idle:begin
				if (inp==next)   
				begin 
					present_state<=inputdata;
				end 
				else
				   present_state<=present_state;
		end
	   inputdata:begin       
				if (inp<=7)   
					begin 
                        sp[2:0]=inp[2:0];     
						present_state<=present_state;
					end 
				else if (inp==negate)
					   begin

							present_state<=present_state;
					   end

				else if (inp==enter)//BCD转2进制.再转BCD显示的补码
					   begin
	
						present_state<=idle;       
					  end                 
					else
						present_state<=present_state;           
		end 
    endcase
end


always@(key_value) 
begin
    case(key_value)
        16:inp=1;
        15:inp=2;
        14:inp=3;
        13:inp=add; //+
        12:inp=4;
        11:inp=5;
        10:inp=6;
        9:inp=sub; //-
        8:inp=7;
        7:inp=8;
        6:inp=9;
        5:inp=mltp; //*
        4:inp=negate;  //符号切换
        3:inp=0;
        2:inp=enter;  //idle
        1:inp=next;   //输入新数字
        0:inp=0;  //没有输入
    endcase
end

/*****************5---波形显示********************/


wire [31:0] trg_cnt;
assign trg_cnt = 32'd1024 - Trigger_cnt;
wave_procs get_wave(
    .clk(clk_50m),
    .clk_adc(Trigger_occur&Trigger_clk),
    .trg_cnt(trg_cnt),
    .vppset(sw[10]),
    .sp(sp),
    .rst_n(rst_n),
    .Hsync(Hsync),
    .Vsync(Vsync),
    .vgaRed(vgaRed),
    .vgaGreen(vgaGreen),
    .vgaBlue(vgaBlue),
    .sample1(Trigger_data),
    .sample2(value_ch2)
);


/*****************6---ILA调试********************/
reg cnt=0;
always @(posedge clk_50m) cnt <= ~cnt;
ila_1 u_ila_1 (
    .clk(clk_50m), // input wire clk
    .probe0(value_ch1), // input wire [11:0]  probe0  
    .probe1(value_filter_ch1), // input wire [11:0]  probe1 
    .probe2(Trigger_data), // input wire [11:0]  probe2 
    .probe3({adc_clk,adc_filter_clk_ch1,Trigger_occur,cnt,8'b0})  ,   // input wire [11:0]  probe3
    .probe4(trg_cnt[29:0])
);







    
endmodule
